1. Field of the Invention
The present invention relates to a technique to reduce noise in a print circuit board mounted with a semiconductor integrated circuit (IC/LSI).
2. Description of the Related Art
As the speed and frequency of a semiconductor integrated circuit (IC/LSI) increase, EMI (Electro Magnetic Interference) as the unwanted radiation of the electro magnetic wave has become an issue. Various factors can cause EMI. Noise generated by the power supply terminal of the IC/LSI is one major factor.
Conventionally, a bypass capacitor is provided to decrease the noise generated by the power supply terminal of the IC/LSI. The bypass capacitor stably supplies power to the IC and simultaneously prevents potential fluctuation at the power supply terminal of the IC, that is, outflow of the noise to the main power supply wiring. This is based on the operation (decoupling) that the noise of the power supply terminal returns to ground through the bypass capacitor. Noise outflow to the main power supply wiring adversely affects a print circuit board over a wide range to induce degradation of EMI. Insertion of the bypass capacitor prevents noise outflow.
As a measure to enhance the noise decoupling effect of the bypass capacitor, a method of providing a chip inductor is arranged to enhance the decoupling effect of the bypass capacitor. As shown in FIG. 2, a component (inductor 1) which increases the impedance is provided to a bypass capacitor 3 on a main power supply wiring 2 side to decrease the impedance of the bypass capacitor 3 relatively, thus enhancing the decoupling effect.
FIG. 3 shows the flow of noise 4 of the circuit in FIG. 2. FIG. 3 shows how the inductor 1 prevents outflow of the noise to the main power supply side.
Based on the same idea as described above, Japanese Patent Laid-Open No. 9-139573 discloses a method of increasing the impedance of the main power supply wiring by considering the arrangement of the wiring.
Recently, however, the conventional method of inserting the inductance cannot often decouple the noise, and the noise often flows out to the main power supply.
The following description can explain this phenomenon.
In recent years, the IC/LSI package size increases. A narrow-pitch, multi-pin QFP and an area grid array represented by a BGA are employed often. Downsizing of electronic devices also progresses. Along with this trend, the component mounting surface of a print circuit board where a bypass capacitor is to be mounted is often the back surface of the surface where an IC/LSI is to be mounted. In this case, the print circuit board must have a via hole to connect the power supply terminal of the IC/LSI to the bypass capacitor.
In a multilayer print circuit board having four or more layers, the via hole is formed to extend through a main power supply conductive layer and ground conductive layer as inner layers. To prevent short-circuiting between the via hole and the ground conductive layer as the inner layer, a portion where no conductor is present, i.e., a clearance hole, is formed concentrically around the via hole in the ground conductive layer.
FIG. 4 is a perspective view schematically showing the respective layers of a print circuit board, and FIG. 5 is a plan view of the respective layers.
Referring to FIGS. 4 and 5, reference numeral 3 denotes a bypass capacitor; 5, a semiconductor device such as an IC or LSI; 6, a main power supply layer; 7, a ground layer; 8, a first power supply via hole; 9, a second power supply via hole; 10, a ground via hole; 12, a first surface layer; and 13, a second surface layer. Reference numerals 18 denote connecting portions which connect via holes to inner-layer conductors, respectively; and 22, clearance holes where no conductors are present to prevent the via holes and the inner-layer conductors from respectively coming into contact with each other.
In order to maintain the electrical path to the bypass capacitor 3 and prevent noise outflow to the main power supply layer 6, the main power supply layer 6 also has the clearance hole 22 around the first power supply via hole 8. In general, the clearance hole 22 has a minimal manufacturable size. This undesirably causes capacitive coupling between the power supply via hole 8 and main power supply layer 6, and a noise current may flow out to the main power supply layer 6 before it reaches the bypass capacitor 3. As a result, the decoupling effect of the bypass capacitor 3 degrades.
FIG. 6 shows a circuit which employs a capacitive coupling 11 by means of the clearance hole 22, and FIG. 7 shows the flow of the noise 4. FIG. 8 also shows the flow of the noise 4 in the perspective view of FIG. 4.
It can be understood that the capacitive coupling 11 between the clearance hole 22 and main power supply layer 6 causes noise outflow to the main power supply layer 6. This phenomenon occurs between the power supply terminal of the IC 5 and the bypass capacitor 3. Even insertion of an inductor 1 to the main power supply side according to the prior art described above cannot solve this phenomenon.